1. Field of the Invention
The present invention relates to a semiconductor device that is suitable for a nonvolatile memory device such as an EEPROM or flash memory that allows data to be rewritten by applying a high voltage to a memory cell.
2. Description of the Related Art
In recent years, EEPROM and flash memory have been widely used for varied program storage or data storage of consumer devices or industrial machinery and so forth. Memory cells constituting EEPROM or flash memory use tunnel currents and hot electrons produced by high voltages (15V, for example) and inject electrons into the floating gate and discharge the electrons from the floating gate. As a result, data rewriting is performed by changing the threshold value of the memory cell.
Furthermore, in general, semiconductor devices fabricated by a semiconductor factory undergo so-called screening testing to remove those semiconductor devices that are probably defective after the same have been shipped with defects. The screening testing is performed under more rigorous conditions than the conditions experienced in normal use, such as high temperature and high voltage conditions beyond the conditions of the warranty, for example. Nonvolatile memory devices such as EEPROM or flash memory also undergo screening testing and a variety of techniques have been proposed such as those that are described in Japanese Patent Application Laid Open No. 2000-182373 and Japanese Patent Application Laid Open No. 2001-250396, for example. The technique described in Japanese Patent Application Laid Open No. 2000-182373 allows high voltages to be obtained in the screening testing and the technique of Japanese Patent Application Laid Open No. 2001-250396 serves to simplify the screening testing.
FIG. 6 shows a block diagram of a conventional nonvolatile memory device 101. The nonvolatile memory device 101 is constituted by a memory cell section 2 in which a plurality of memory cells are provided, an X decoder 5 to which an address signal of a lower address line is input and which selects one word line (or control line) (not shown) of the memory cell section 2, a Y decoder 6 to which an address signal of an upper address line is input and which selects certain memory cells that perform reading or writing within memory cells linked to one word line (or control line), a Y gate 3 to which the output signal of the Y decoder 6 is input and which connects the selected memory cells and a subsequently described data I/O circuit 4, a data I/O circuit 4 that reads data of the memory cells, outputs the data to a data line, and rewrites the memory cell data in accordance with the data signal of the data line; and a high-voltage production circuit 7 that produces a high voltage for data rewriting and outputs the high voltage to the node A in FIG. 6. When the memory cell data are rewritten, the high voltage output by the high voltage production circuit 7 is applied from node A to each of the memory cells of the memory cell section 2 via the X decoder 5 or data I/O circuit 4.
However, the high voltage output by the high voltage production circuit 7 sharply rises at time to when the data rewriting starts as shown by the waveform a of FIG. 7. The sharp rise exerts excess stress on the memory cell and, as a result, the lifespan of the memory cell is shortened.
Further, the elements for high voltage used by peripheral circuits of the memory cell section such as the high voltage production circuit 7 (specifically, the N-type or P-type MOS transistor or the like) operate close to the withstand voltage limit. Therefore, tests using higher high voltages produced or input from the outside in the screening testing were difficult to perform in practice. Hence, in reality, the testing of a memory cell section that includes a plurality of memory cells is a test that implements rigorous conditions such as the supply voltage (not the applied high voltage) and temperature instead of raising the applied high voltage, and the accuracy of the screening testing has been inadequate.